Semiconductor device

ABSTRACT

A semiconductor device includes a first semiconductor chip and a second semiconductor chip, and wherein the first semiconductor chip includes a plurality of first bonding pads, and the second semiconductor chip includes a plurality of second bonding pads for coupling respectively to the first bonding pads by wire-bonding coupling and at least one third bonding pad for enabling relay coupling of a corresponding second bonding pad to at least one predetermined first bonding pad which is arranged along the second bonding pads and included in the first bonding pads without crossing another wire in the wire-bonding coupling.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a Continuation application of U.S. patentapplication Ser. No. 14/639,018, filed on Mar. 4, 2015, which is basedon the disclosure of Japanese Patent Application No. 2014-055009 filedon Mar. 18, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

The present invention relates to a semiconductor device, and moreparticularly, to a semiconductor device in which a plurality ofsemiconductor chips is mounted.

BACKGROUND

As a key technology for realizing reductions in size, weight, andthickness of electronic devices, various packaging technologies have sofar been developed for semiconductor devices, in order to realize thehigh-density packaging of the semiconductor chips.

As a technology for the packaging structure of the semiconductor devicesand for reducing the area necessary for packaging onto the motherboard,there is a pin insertion type package, such as DIP (Dual InlinePackage). There have been developed a surface mount package (SOP (SmallOutline Package)), with outer leads and also a package (BGA (Ball GridArray)), in which outer output terminals are arranged in matrix on thelower surface of package.

As a technology for realizing the high-density packaging by reducing thearea ratio of the package to the semiconductor chips, there have beenmade some attempts, such as narrow pitching of the outer outputterminals by the minuteness of the substrate wiring and also reductionof the package size.

Further, there have been developed technologies, such as a multi-chippackage and a chip-stacked package. In the multi-chip package, aplurality of semiconductor chips are gathered and packed in a singlepackage. The chip-stacked package, as one kind of multi-chip package,has a plurality of semiconductor chips stacked therein for realizing thefurther high-density packaging. Of the multi-chip packages, a System InPackage (SIP) has been developed, as one system which has realized thesystematization by enclosing the plurality of semiconductor chips havingdifferent functions in a single package.

In this SIP technology, it is necessary to shape the wiring couplingbetween the chips for the reduction of the package, and there has beenproposed a system for coupling the wiring using a relay member, to becalled a silicon interposer (U.S. Pat. No. 4,615,189 and JapaneseUnexamined Patent Publication No. Hei 5(1993)-102222).

However, if the relay member, such as a silicon interposer, is used, itcauses a problem of increasing the cost in the designing andmanufacturing of the relay member.

Japanese Unexamined Patent Publication No. 2008-177265 proposes a systemfor shaping the wiring coupling by providing relay members respectivelybetween bonding pads and inner leads of a semiconductor device. For thisrelay member, there has been proposed a system for forming the member bystacking an electrically conducting layer on the surface of thesemiconductor device. In this case, a problem is an increase in the costof designing and manufacturing it.

SUMMARY

To solve the above problem, there is provided a semiconductor devicewhich can easily achieve wiring coupling between chips using a simplestructure.

Other tasks and new features will be obvious from the descriptions ofthe present specification and attached drawings.

According to an embodiment, there is provided a semiconductor devicewhich includes a first semiconductor and second semiconductor chipsmounted on a package substrate. The first semiconductor chip includes aplurality of first bonding pads which are arranged along one side of thefirst semiconductor chip. The second semiconductor chip includes aplurality of second bonding pads and at least one third bonding pad. Thesecond bonding pads are arranged along one side of the secondsemiconductor chip and for coupling respectively to the first bondingpads by wire-bonding coupling. The at least one third bonding pad is forenabling relay coupling of a corresponding second bonding pad to atleast one predetermined first bonding pad which is arranged along thesecond bonding pads and included in the first bonding pads withoutcrossing another wire in the wire-bonding coupling.

According to an embodiment, the above structure easily enables thewiring coupling between the chips using a simple structure.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram for explaining a structure of a semiconductor device1 according to a First Embodiment.

FIG. 2 is another diagram for explaining the structure of thesemiconductor device 1 according to the First Embodiment.

FIG. 3 is a diagram for explaining a semiconductor device as acomparative example 1 to be compared with the semiconductor device 1according to the First Embodiment.

FIG. 4 is a diagram for explaining a semiconductor device as acomparative example 2 to be compared with the semiconductor device 1according to the First Embodiment.

FIG. 5 is a diagram for explaining another semiconductor device as acomparative example 3 to be compared with the semiconductor deviceaccording to the First Embodiment.

FIG. 6 is a diagram for explaining wire-bonding coupling of thesemiconductor device according to the First Embodiment.

FIG. 7 is a diagram for explaining another wire-bonding coupling of thesemiconductor device 1 according to the First Embodiment.

FIG. 8 is a diagram for explaining wire-bonding coupling of thesemiconductor device 1 according to a modification of the FirstEmbodiment.

FIG. 9 is a diagram for explaining wire-bonding coupling of thesemiconductor device 1 according to a Second Embodiment.

FIG. 10 is a diagram for explaining wire-bonding coupling of asemiconductor device 1 according to a modification of the SecondEmbodiment.

FIG. 11 is a diagram for explaining wire-bonding coupling of asemiconductor device 1 according to a Third Embodiment.

DETAILED DESCRIPTION

Preferred embodiments of the present invention will now specifically bedescribed with reference to the drawings. The same or correspondingparts in the drawings will be identified with the same referencenumerals, and will not repeatedly be described.

First Embodiment

FIG. 1 is a diagram for explaining a structure of a semiconductor device1 according to a First Embodiment.

In the illustration of FIG. 1, in this embodiment, the semiconductordevice 1 is viewed from the upper surface. The semiconductor device 1 isa System In Package (SIP) with a plurality of semiconductor chipsmounted thereon.

In this embodiment, descriptions will be made to a first semiconductorchip and a second semiconductor chip as the plurality of semiconductorchips by way of example. In this embodiment, the first semiconductorchip is a memory chip including a storage device. The secondsemiconductor chip is a logic chip including a logic circuit whichexecutes a predetermined calculation process.

In this case, the semiconductor device 1 includes a package substratePK1, a semiconductor chip CPA stacked on an upper layer of this packagesubstrate PK1, and a semiconductor chip MX stacked on an upper layer ofthe semiconductor chip CPA.

In each of the package substrate PK1 and the semiconductor chips CPA andMX, a plurality of bonding pads PD are provided for wire-bondingcoupling. The illustration is made on a state before the wire-bondingcoupling is made.

FIG. 2 is another diagram for explaining a structure of thesemiconductor device according to the First Embodiment. In theillustration of FIG. 2, in this embodiment, the semiconductor device 1is viewed from the side surface.

The semiconductor device 1 includes a package substrate PK1, asemiconductor chip CPA stacked on an upper surface of this packagesubstrate PK1, and a semiconductor chip MX stacked on an upper layer ofthe semiconductor chip CPA.

The package substrate PK1 and the semiconductor chip CPA are coupled bywire bonding. The semiconductor chip CPA and the semiconductor chip MXare coupled by wire bonding.

As a result, wiring coupling is achieved between the chips, thusenabling to realize a desired semiconductor device.

FIG. 3 is a diagram for explaining a semiconductor device as acomparative example 1 to be compared with the semiconductor device 1according to the First Embodiment.

As illustrated in FIG. 3, a semiconductor chip 100 includes bonding padsPD for voltages VDD and VSS, data D0 to D7, and a control signal CTL.

Similarly, a semiconductor chip 104 and a package substrate 106 includebonding pads PD for voltages for voltages VDD and VSS, data D0 to D7,and a control signal CTL.

The wire-bonding coupling is a technique for coupling the correspondingbonding pads between the chips by wire (lead).

As illustrated in this embodiment, the semiconductor chip 104 has aplurality of bonding pads corresponding to the plurality of bonding padsof the semiconductor chip 100 which transmits and receives signals toand from other chips through wire bonding coupling. Further, thesemiconductor chip 104 has a plurality of bonding pads corresponding toa plurality of bonding pads of the package substrate 106 which transmitsand receives signals to and from other chips through wire bondingcoupling.

The bonding pad corresponding to the signal D0 of the semiconductor chipand the bonding pad corresponding to the signal D0 of the semiconductorchip 104 are coupled by wire bonding. The bonding pad corresponding tothe signal D0 of the semiconductor chip 104 and the bonding padcorresponding to the signal D0 of the package substrate 106 are coupledby wire bonding. The same applies to those bonding pads corresponding toother signals. In the illustrated case, the bonding pads correspondingto the voltages VDD and VSS are shared in the semiconductor chip 104.

In the illustrated case, the same signal array of the bonding pads PD isapplied in the semiconductor chip 100, the semiconductor chip 104, andthe package substrate 106.

In this structure, the plurality of wires for the wire-bonding couplingenable the coupling of the opposed corresponding bonding pads withoutcrossing each other.

FIG. 4 is a diagram for explaining a semiconductor device as acomparative example 2 to be explained with the semiconductor device 1according to the First Embodiment.

As a comparison with the semiconductor device of FIG. 3, FIG. 4illustrates a case where the semiconductor chip 100 has been changed toa semiconductor chip 101.

As seen from this illustration, in the semiconductor chip 101, positionsof the bonding pads corresponding to the voltages VDD and VSS differfrom those of the semiconductor chip 100. Specifically, in theillustrated case, the positions of the bonding pads corresponding to thevoltages VDD and VSS are switched. In the structure of the semiconductordevice in the comparative example 2, the positional relationship of thebonding pad for the voltage VDD and the bonding pad for the voltage VSShas been changed. Thus, when the wire-bonding coupling is achieved inaccordance with a normal technique, they cross other wires. In thisstructure, because the wires may possibly be short-circuited, somechange needs to be made in the design. That is, to correspond to thesignal array of the bonding pads of the semiconductor chip 101, it isnecessary to change the signal arrays of the bonding pads of thesemiconductor chip 104 and the package substrate 106 in accordance withthe pattern of the semiconductor chip 101. This involves a change in themanufacturing processes, and causes an increase in the cost.

FIG. 5 is a diagram for explaining another semiconductor device as acomparative example 3 to be compared with the semiconductor device 1according to the First Embodiment.

As a comparison with the semiconductor device of FIG. 3, FIG. 5illustrates a case where the semiconductor chip 100 has been changed toa semiconductor chip 102.

As illustrated, in the semiconductor chip 102, positions of the bondingpads for the voltages VDD and VSS differ from those of the semiconductorchip 100. Specifically, in the illustrated case, the bonding pads forthe voltages VDD and VSS are provided near the center of one side of thesemiconductor device 1.

In the structure of the semiconductor device in the comparative example3, the positional relationship of the bonding pad for the voltage VDDand the bonding pad for the voltage VSS has been changed. Thus, if thewire-bonding coupling is made accordance with a normal technique, theycross other wires. In this structure, the wire may possibly beshort-circuited. Thus, it is necessary to change the design. That is, tocorrespond to the signal array of the bonding pads of the semiconductorchip 102, it is necessary to change the signal arrays of the bondingpads of the semiconductor chip 104 and the package substrate 106 inaccordance with the pattern of the semiconductor chip 102. This involvesa change in the manufacturing process, and causes an increase in thecost.

Descriptions will now be made to a technique for wire-bonding couplingof the semiconductor device 1 according to the First Embodiment.

FIG. 6 is a diagram for explaining the wire-bonding coupling of thesemiconductor device 1 according to the First Embodiment.

As illustrated in FIG. 6, the semiconductor chip MX includes bondingpads PD for voltages VDD and VSS, data D0 to D7, and a control signalCTL.

In this embodiment, the signal array is made along one side of thesemiconductor chip, sequentially in the order of the voltage VSS, thedata D0 to D7, the control signal CTL, and the voltage VDD. Thissemiconductor chip MX has the same signal array as that of thesemiconductor chip 101.

The signal array of the bonding pads PD is the same signal array as thatof the semiconductor chip CPA and the package substrate PK1. In theillustration, the signal array is the same as that of the semiconductorchips 104 and 106.

In this structure, the wire bonding coupling between the semiconductorchip CPA and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads by wire.

The semiconductor chip CPA and the semiconductor chip MX are coupled bywire bonding through bonding pads for enabling relay coupling.

In this embodiment, two bonding pads MT1 and MT2, as bonding pads forenabling relay coupling, are arranged along the plurality of bondingpads PD arranged along one side of the semiconductor chip. The bondingpads MT1 and MT2 are used in a metal wiring layer on the same layer asthat of the bonding pads for other signals. The bonding pads MT1 and MT2are arranged parallelly along the plurality of bonding pads PD arrangedalong one side of the semiconductor chip.

In this embodiment, the bonding pad MT1 is used as a bonding pad forrelaying the voltage VSS. The bonding pad MT2 is used as a bonding padfor relaying the voltage VDD.

Specifically, the bonding pad for the voltage VSS in the semiconductorchip is coupled to the bonding pad MT1 by wire bonding. The bonding padMT1 is coupled to the bonding pad for the voltage VSS in thesemiconductor chip CPA by wire bonding, and then coupled to the bondingpad for the voltage VSS corresponding to the package substrate PK1 bywire bonding.

It is possible to achieve the wiring coupling without crossing otherwires, by achieving the wire-bonding coupling through the bonding padsfor relaying.

The bonding pad for the voltage VDD in the semiconductor chip MX iscoupled to the bonding pad MT2 by wire bonding. The bonding pad MT2 iscoupled to the bonding pad for the voltage VDD in the semiconductor chipCPA by wire bonding, and then coupled to the bonding pad for the voltageVDD corresponding to the package substrate PK1 by wire bonding.

It is possible to achieve the wiring coupling without crossing otherwires, by achieving the wire-bonding coupling through the bonding wirefor relaying.

There is no need to make the wiring coupling in a state of crossingother wires (wire) by this wire bonding coupling, and it is possible toachieve the wiring coupling using a simple technique without changingthe design.

The bonding pads MT1 and MT2 provided in the semiconductor chip CPA maybe used in a metal wiring layer on the same layer as that of the bondingpads for other signals. Thus, there is no need to change (add) themanufacturing processes for manufacturing the bonding pads MT1 and MT2,and it is possible to suppress an increase in the cost and achieve thewire-bonding coupling using a simple technique.

FIG. 7 is a diagram for explaining another wire-bonding coupling of thesemiconductor device 1 according to this First Embodiment.

As illustrated in FIG. 7, a semiconductor chip MY includes bonding padsPD for voltages VDD and VSS, data D0 to D7, and a control signal CTL.

In this embodiment, the signal array is made along one side of thesemiconductor chip, sequentially in the order of the data D0 to D3, thevoltage VDD, the voltage VSS, the data D4 to D7, and the control signalCTL. This semiconductor chip MY has the same signal array as that of thesemiconductor chip 102.

The signal array of the bonding pads PD is the same as that of thesemiconductor chip CPA and the package substrate PK1. In the illustratedcase, the signal array is the same as that of the semiconductor chips104 and 106.

In this structure, the wire-bonding coupling between the semiconductorchip CPA and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads with each other by wire.

The semiconductor chip CPA and the semiconductor chip MX are coupled bywire bonding through the bonding pads for enabling relay coupling.

In this embodiment, as the bonding pads for enabling relay coupling, twobonding pads MT1 and MT2 are arranged along the plurality of bondingpads PD arranged along one side of the semiconductor chip.

In this embodiment, the bonding pad MT1 is used as a bonding pad forrelaying the voltage VDD. The bonding pad MT2 is used as a bonding padfor relaying the voltage VSS.

Specifically, the bonding pad for the voltage VDD in the semiconductorchip MY is coupled to the bonding pad MT1 by wire bonding. The bondingpad MT1 is coupled to the bonding pad of the semiconductor chip CPA bywire bonding, and then coupled to the bonding pad for the voltage VDD ofthe package substrate PK1 by wire bonding.

It is possible to achieve wiring coupling without crossing other wires,by achieving the wire bonding coupling through the bonding pad forrelaying.

The bonding pad for the voltage VSS of the semiconductor chip MY iscoupled to the bonding pad MT2 by wire bonding. The bonding pad MT2 iscoupled to the bonding pad for the voltage VSS of the semiconductor chipCPA by wire bonding, and then coupled to the bonding pad for the voltageVSS of the package substrate PK1 by wire bonding.

It is possible to achieve the wiring coupling without crossing otherwires, by achieving the wire-bonding coupling through the bonding padfor relaying.

There is no need to make the wiring coupling in a state of crossingother wires by this wire-bonding coupling, and it is possible to achievethe wiring coupling using a simple technique without changing thedesign.

The bonding pads MT1 and MT2 provided in the semiconductor chip CPA maybe used in a metal wiring layer on the same layer as that of the bondingpads for other signals. Thus, there is no need to change (add) themanufacturing processes for manufacturing the bonding pads MT1 and MT2,and it is possible to suppress an increase in the cost and achieve thewire-bonding coupling using a simple technique.

Modification

In the above, the descriptions have been made to the case where the twobonding pads MT1 and MT2 are used. However, this number is not limitedto two, and a plurality of bonding pads can be used.

FIG. 8 is a diagram for explaining the wire-bonding coupling of thesemiconductor device 1 according to the modification of the FirstEmbodiment.

As illustrated in FIG. 8, a semiconductor chip MZ includes bonding padsPD for voltages VDD and VSS, data D0 to D7, and a control signal CTL.

In this embodiment, the signal array is made along one side,sequentially in the order of the control signal CTL, the data D0 to D3,the voltage VDD, the voltage VSS, and the data D4 to D7.

In the illustrated case, the signal array of the bonding pads PD is thesame as that in the semiconductor chip CPA and the package substratePK1.

In this structure, the wire-bonding coupling between the semiconductorchip CPA and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads with each other by wire.

The semiconductor chip CPA and the semiconductor chip MZ are coupled bywire bonding through bonding pads for enabling relay coupling.

In this embodiment, as bonding pads for enabling relay coupling, threebonding pads MT1, MT2, and MT2# are arranged along a plurality ofbonding pads PD arranged along one side of the semiconductor chip. Thebonding pads MT1, MT2, and MT2# are used in a metal wiring layer on thesame layer as that of the bonding pads for other signals.

In this embodiment, the bonding pad MT1 is used as a bonding pad forrelaying the control signal CTL. The bonding pad MT2 is used as abonding pad for relaying the voltage VDD. The bonding pad MT2# is usedas a bonding pad for relaying the voltage VSS.

Specifically, the bonding pad for the control signal CTL in thesemiconductor chip MZ is coupled to the bonding pad MT1 by wire bonding.The bonding pad MT1 is coupled to the bonding pad for the control signalCTL in the semiconductor chip CPA by wire bonding. The bonding pad forthe control signal CTL of the semiconductor chip CPA is coupled to thebonding pad for the control signal CTL corresponding to the packagesubstrate PK1 by wire bonding.

The bonding pad for the voltage VDD in the semiconductor chip MZ iscoupled to the bonding pad MT2 by wire bonding. The bonding pad MT2 iscoupled to the bonding pad for the voltage VDD in the semiconductor chipCPA by wire bonding, and then coupled to the bonding pad for the voltageVDD corresponding to the package substrate PK1 by wire bonding.

The bonding pad for the voltage VSS in the semiconductor chip MZ iscoupled to the bonding pad MT2# by wire bonding. The bonding pad MT2# iscoupled to the bonding pad for the voltage VSS in the semiconductor chipCPA by wire bonding, and then coupled to the bonding pad for the voltageVSS corresponding to the package substrate PK1 by wire bonding.

It is possible to achieve the wiring coupling without crossing otherwires, by making the wiring-bonding coupling through the bonding pad forrelaying.

There is no need to make the wiring coupling in a state of crossingother wires by this wire-bonding coupling, and it is possible to achievethe wiring coupling using a simple technique without changing thedesign.

The bonding pads MT1, MT2, and MT2# provided in the semiconductor chipCPA may be used in a metal wiring layer on the same layer as that of thebonding pads for other signals. Thus, there is no need to change (add)the manufacturing processes for manufacturing the bonding pads MT1 andMT2, and it is possible to suppress an increase in the cost and achievethe wire-bonding coupled using a simple technique.

At this point, the bonding pads MT2 and MT2# are arranged in seriesalong the plurality of bonding pads PD arranged along one side of thesemiconductor chip.

In a manufacturing process, a region between the bonding pads MT2 andMT2# (an electrically insulated part) is masked not to form a metallayer. This enables easy formation of the bonding pads by the designwithout forming the metal layer in the masked part.

In this embodiment, the descriptions have been made to the case wherethe three bonding pads MT1, MT2, and MT2# are arranged along theplurality of bonding pads PD arranged along one side of thesemiconductor chip. However, not limited to this, it is possible toarrange further more bonding pads.

Second Embodiment

In this above-described First Embodiment, the descriptions have beenmade to the case where the positions of the bonding pads for thevoltages VDD and VSS of the semiconductor chip MX differ between thesemiconductor chip CPA and the package substrate PK1. Descriptions willnow be made to a case where the position of the bonding pad for thecontrol signal CTL differs from those in the semiconductor chip CPA andthe package substrate PK1.

FIG. 9 is a diagram for explaining the wire-bonding coupling of thesemiconductor device 1 according to the Second Embodiment.

As illustrated in FIG. 9, the semiconductor chip MX# includes bondingpads PD for voltages VDD and VSS, data D0 to D7, and a control signalCTL.

In this embodiment, the signal array is made along one side,sequentially in the order of the voltage VSS, the control signal CTL,the data D0 to D7, and the voltage VDD.

The signal array of the bonding pads PD is substantially the same asthat in the semiconductor chip CPA and the package substrate PK1, andalso the same as that of the semiconductor chips 104 and 106.

In this structure, the wire-bonding coupling between the semiconductorchip CPA and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads with each other by wire.

The semiconductor chip CPA and the semiconductor chip MX# are coupledwith each other by wire, through bonding pads for enabling relaycoupling.

In this embodiment, as bonding pads for enabling relay coupling, twobonding pads MT1 and MT2 are arranged along the plurality of bondingpads PD.

The bonding pad MT1 is used as a bonding pad for relaying the controlsignal CTL. The bonding pad MT2 is used as a bonding pad for relayingthe voltage VDD.

In the illustrated case, for the wire-bonding coupling with the bondingpad for the voltage VSS of the semiconductor chip MX#, on the side ofthe package substrate PK1, the coupling is made by extending the bondingpad, for enabling the wire-bonding coupling with the semiconductor chipMX# in a position not crossing other wires.

The bonding pad for the control signal CTL of the semiconductor chip MX#is coupled to the bonding pad MT1 by wire bonding, while the bonding padMT1 is coupled to the bonding pad for the control signal CTL of thepackage substrate PK1 by wire bonding.

The bonding pad for the voltage VDD of the semiconductor chip MX# iscoupled to the bonding pad MT2 by wire bonding, while the bonding padMT2 is coupled to the bonding pad for the voltage VDD of the packagesubstrate PK1 by wire bonding.

There is no need to make the wiring coupling while crossing other wiresby the wire bonding coupling, and it is possible to achieve the wiringcoupling using a simple technique without changing the design.

In this structure, because the arrangements of the three bonding padsfor the voltages VDD and VSS and the control signal CTL of thesemiconductor chip MX# differ from one another, three bonding pads arenecessary for enabling the relay coupling. However, by extending thebonding pad for the voltage VSS in the package substrate PK1, it ispossible to suppress an increase in the cost and achieve thewire-bonding coupling using a simple technique, without performing anadditional manufacturing process.

Modification

FIG. 10 is a diagram for explaining the wire-bonding coupling of thesemiconductor device 1 according to a modification of the SecondEmbodiment.

As illustrated in FIG. 10, the semiconductor chip MX# includes bondingpads PD for voltages VDD and VSS, data D0 to D7, and a control signalCTL.

In this embodiment, the signal array is made along one side,sequentially in the order of the voltage VSS, the control signal CTL,the data D0 to D7, and the voltage VDD.

In the illustrated case, the signal array of the bonding pads PD issubstantially the same signal array in the semiconductor chip CPA andthe package substrate PK1, and is the same as that in the semiconductorchips 104 and 106.

In this structure, the wire-bonding coupling of the semiconductor chipCPA and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads by wire.

The semiconductor chip CPA and the semiconductor chip MX# are coupled bywire bonding through bonding pads for enabling relay coupling.

In this embodiment, as bonding pads for enabling relay coupling, threebonding pads MT1, MT2, and MT2# are arranged along a plurality ofbonding pads PD.

The bonding pad MT1 is used as a bonding pad for relaying the controlsignal CTL. The bonding pad MT2 is used as a bonding pad for relayingthe voltage VSS. The bonding pad MT2# is used as a bonding pad forrelaying the voltage VDD.

The bonding pad for the control signal CTL of the semiconductor chip MX#is coupled to the bonding pad MT1 by wire bonding. The bonding pad MT1is coupled to the bonding pad for the control signal CTL of thesemiconductor chip by wire bonding, and then coupled to the bonding padfor the control signal CTL of the package substrate PK1 by wire bonding.

The bonding pad for the voltage VDD of the semiconductor chip MX# iscoupled to the bonding pad MT2# by wire bonding. The bonding pad MT2# iscoupled to the bonding pad for the voltage VDD of the semiconductor chipby wire bonding, and then coupled to the bonding pad for the voltage VDDof the package substrate PK1 by wire bonding.

The bonding pad for the voltage VSS of the semiconductor chip MX# iscoupled to the bonding pad MT2 by wire bonding. The bonding pad MT2 iscoupled to the bonding pad for the voltage VSS of the semiconductor chipby wire bonding, and then coupled to the bonding pad for the voltage VSSof the package substrate PK1 by wire bonding.

There is no need to make the wiring coupling in a state of crossingother wires by this wire bonding coupling, and it is possible to achievethe wiring coupling using a simple technique without changing thedesign. The bonding pads MT1, MT2, and MT2# provided in thesemiconductor chip CPA may be used the metal wiring layer on the samelayer as the bonding pads for other signals. Thus, there is no need tochange (add) the manufacturing processes for manufacturing the bondingpads MT1 and MT2, and it is possible to suppress an increase in the costand make the wire-bonding coupling using a simple technique.

As compared with the structure of the above Second Embodiment, there isno need to make the wire coupling directly between the bonding pad forthe voltage VSS of the semiconductor chip MX# and the bonding pad forthe voltage VSS of the package substrate PK1. The relaying is donethrough the bonding pad MT2. Thus, it enables to shorten the wire lengthand facilitates the loop control.

Third Embodiment

The above descriptions have been made to the case where the positions ofthe bonding pads for the voltages VDD and VSS of the semiconductor chipMX stacked on the upper layer differ from the semiconductor chip CPA andthe package substrate PK1. In the Third Embodiment, descriptions willnow be made to a case where positions of the bonding pads of thesemiconductor chip are different from others, in the intermediateposition.

FIG. 11 is a diagram for explaining the wire-bonding coupling of thesemiconductor device 1 according to the Third Embodiment.

As illustrated in FIG. 11, a semiconductor chip MP includes bonding padsPD for voltages VDD and VSS, data D0 to D7, and a control signal CTL.

In this embodiment, the signal array is made along one side,sequentially in the order of the voltage VDD, the data D0 to D7, thecontrol signal CTL, the voltage VSS.

In the illustrated case, the signal array of the bonding pads PD is thesame signal array in the semiconductor chip MP and the package substratePK1, but the signal array of a semiconductor chip CPA# is differenttherefrom.

The semiconductor chip CPA# includes bonding pads PD for voltages VDDand VSS, data D0 to D7, and a control signal CTL.

In this embodiment, the signal array is made along one side,sequentially in the order of the voltage VSS, the data D0 to D7, thecontrol signal CTL, and the voltage VDD.

In this structure, the wire-bonding coupling between the semiconductorchip CPA# and the package substrate PK1 can be achieved by coupling theopposed corresponding bonding pads.

The wire-bonding coupling between the semiconductor chip CPA# and thesemiconductor chip MP can be achieved by coupling the opposedcorresponding bonding pads with each other.

A part of the bonding pads are coupled by wire bonding through thebonding pads for enabling relay coupling.

In this embodiment, as the bonding pads for enabling relaying, twobonding pads MT1 and MT2 are arranged along the plurality of bondingpads PD.

The bonding pad MT1 is used as a bonding pad for relaying the voltageVDD. The bonding pad MT2 is used as a bonding pad for relaying a voltageVSS.

Specifically, the bonding pad for the voltage VDD in the semiconductorchip MP is coupled to the bonding pad MT1 by wire bonding. The bondingpad MT1 is coupled to the bonding pad for the voltage VDD of thesemiconductor chip CPA# by wire bonding, and then coupled to acorresponding bonding pad for the voltage VDD in the package substratePK1 by wire bonding.

The bonding pad for the voltage VSS in the semiconductor chip MP iscoupled to the bonding pad MT2 by wire bonding. The boding pad MT2 iscoupled to the bonding pad for the voltage VDD in the package substratePK1 by wire bonding, and then coupled to a corresponding bonding pad forthe voltage VSS in the semiconductor chip CPA# by wire bonding.

There is no need to make the wiring coupling in the state of crossingother wires by the wire-bonding coupling, and it is possible to achievethe wiring coupling using a simple technique without changing thedesign.

The bonding pads MT1 and MT2 provided in the semiconductor chip CPA maybe used in the metal wiring layer on the same layer as those bondingpads for other signals. Thus, this is no need to change (add) themanufacturing processes for manufacturing the bonding pads MT1 and MT2,and it is possible to suppress an increase in the cost and achieve thewire-bonding coupling using a simple technique.

The above descriptions have been made to a stack type SIP in which thefirst and second semiconductor devices are stacked onto the packagesubstrate. However, it is not limited to the stack type SIPs, and isapplicable similarly to planar arranged SIPs arranged on the same planeor SIPs using any of these.

In the above-described embodiments, the descriptions have been made tothe case where mainly two bonding pads MT1 and MT2 are arranged alongone side of the semiconductor chip. However, one bonding pad ispossible, or a plurality of bonding pads is possibly provided. Thebonding pads may be provided along one side out of four sides of thesemiconductor chip, or may be provided respectively along the sidesthereof.

In the embodiments, the descriptions have been made to the structure inwhich bonding pads for relaying are arranged between the plurality ofbonding pads of the first semiconductor chip and the plurality ofbonding pads of the second semiconductor chip. However, it is notlimited to this structure. For example, in a possible structure, thebonding pads for relaying may be arranged between the plurality ofbonding pads of the package substrate and the plurality of bonding padsof the second semiconductor chip, and its arrangement is notparticularly limited.

Accordingly, the inventions of the present inventors have specificallybeen described based on the preferred embodiments. However, the presentinvention is not limited to the preferred embodiments, and, needless tosay, various changes may be made thereto without departing from thescope of the subject matter.

What is claimed is:
 1. A semiconductor device comprising: a firstsemiconductor chip and a second semiconductor chip, and wherein thefirst semiconductor chip includes a plurality of first bonding pads, andthe second semiconductor chip includes a plurality of second bondingpads for coupling respectively to the first bonding pads by wire-bondingcoupling and at least one third bonding pad for enabling relay couplingof a corresponding second bonding pad to at least one predeterminedfirst bonding pad which is arranged along the second bonding pads andincluded in the first bonding pads without crossing another wire in thewire-bonding coupling.
 2. The semiconductor device according to claim 1,wherein each of the first bonding pads includes a signal pad.
 3. Thesemiconductor device according to claim 1, further comprising: a packagesubstrate over which the first semiconductor chip and the secondsemiconductor chip are mounted, wherein the first semiconductor chipincludes the first bonding pads arranged along one side of the firstsemiconductor chip, the package substrate is arranged along one side ofthe substrate, and includes second bonding pads to be coupled to thefirst bonding pads by wire-bonding coupling, and the secondsemiconductor chip includes at least one third bonding pad for enablingrelay coupling of a corresponding second bonding pad by wire-bondingcoupling to at least one predetermined first bonding pad arranged alongthe second bonding pads and included in the first bonding pads withoutcrossing another wire in the wire-bonding coupling.
 4. The semiconductordevice according to claim 2, wherein each of the first bonding padsincludes a power source pad.
 5. The semiconductor device according toclaim 1, wherein the at least one third bonding pad is arranged betweenthe first bonding pads and the second bonding pads.
 6. The semiconductordevice according to claim 1, wherein the third bonding pad includes aplurality of third bonding pads, and the plurality of third bonding padsare arranged parallelly along the second bonding pads.
 7. Thesemiconductor device according to claim 1, wherein the third bonding padincludes a plurality of third bonding pads, and the plurality of thirdbonding pads are arranged in series along the second bonding pads. 8.The semiconductor device according to claim 1, wherein the firstsemiconductor chip includes a memory chip having a storage cell storingdata.
 9. The semiconductor device according to claim 1, wherein thesecond semiconductor chip includes a logical chip having a logiccircuit.
 10. The semiconductor device according to claim 1, wherein thefirst bonding pads, the second bonding pads, and the at least one thirdbonding pad are formed in a same metallization layer.
 11. Asemiconductor device, comprising: a first semiconductor chip and asecond semiconductor chip, and wherein the first semiconductor chipincludes a plurality of first pads, and the second semiconductor chipincludes a plurality of second pads for coupling respectively to thefirst pads by wire coupling and at least one third pad for enablingrelay coupling of a corresponding second pad to at least onepredetermined first pad which is arranged along the second pads andincluded in the first pads without crossing another wire in the wirecoupling.
 12. The semiconductor device according to claim 11, whereineach of the first pads includes a signal pad.
 13. The semiconductordevice according to claim 11, further comprising: a package substrateover which the first semiconductor chip and the second semiconductorchip are mounted, and wherein the first semiconductor chip includes thefirst pads arranged along one side of the first semiconductor chip, thepackage substrate includes along one side thereof second pads to becoupled to the first pads by wire coupling, and the second semiconductorchip includes at least one third pad for enabling relay coupling of acorresponding second pad by wire coupling to at least one predeterminedfirst pad arranged along the second pads and included in the first padswithout crossing another wire in the wire coupling.
 14. Thesemiconductor device according to claim 12, wherein each of the firstpads includes a power source pad.
 15. The semiconductor device accordingto claim 11, wherein the at least one third pad is arranged between thefirst pads and the second pads.
 16. The semiconductor device accordingto claim 11, wherein the at least one third pad includes a plurality ofthird pads, and the plurality of third pads are arranged parallellyalong the second pads.
 17. The semiconductor device according to claim11, wherein the at least one third pad includes a plurality of thirdpads, and the plurality of third pads are arranged in series along thesecond pads.
 18. The semiconductor device according to claim 11, whereinthe first semiconductor chip includes a memory chip having a storagecell storing data, and wherein the second semiconductor chip includes alogical chip having a logic circuit.
 19. The semiconductor deviceaccording to claim 11, wherein the first pads, the second pads, and theat least one third pad are formed in a same metallization layer.
 20. Amethod of forming a semiconductor device, said method comprising:mounting a first semiconductor chip and a second semiconductor chip overa package substrate, wherein the first semiconductor chip includes aplurality of first bonding pads; arranging the first bonding pads alongone side of the first semiconductor chip, wherein the secondsemiconductor chip includes a plurality of second bonding pads;arranging the plurality of second bonding pads along one side of thesecond semiconductor chip; coupling the plurality of second bonding padsrespectively to the first bonding pads by wire-bonding coupling; andenabling, by at least one third bonding pad, relay coupling of acorresponding second bonding pad to at least one predetermined firstbonding pad which is arranged along the second bonding pads and includedin the first bonding pads without crossing another wire in thewire-bonding coupling.